The present invention relates in general to data processing systems, and in particular, to input/output (I/O) communication between a microprocessor and external system elements.
Microprocessors chips (integrated circuits) have been increasing in complexity wherein more of a computer system""s function has been integrated onto the microprocessor chip. However, the performance of a chip is dependent on the flow of information, instructions and data. As processor speeds have increased there is a corresponding need to provide data and instructions to the processor faster. Memory is one of the system elements that has increasing demands for bandwidth in communicating with a microprocessor chip. Increasing memory access speed has always incurred increased cost. For years memory has been partitioned into performance elements. Cache memory is high speed memory that is loaded with information most accessed by the microprocessor. Cache memory is the fastest and is usually placed on the microprocessor chip in high performance systems. Cache memory is usually static RAM with the highest speed access, the most power, highest cost and most area per bit of all the memory on a chip. Because memory bandwidth and thus cache size increase with processor speed, some high speed memory has to be placed off the microprocessor chip. Including all required high speed memory on a chip would cause the chip size to increase, thus decreasing the yield and increasing the cost above acceptable limits for a given design.
Some microprocessor designs use bi-directional buses on the input and output (I/O) lines as a way to reduce the number of I/O drivers and pins for a given design. Since bi-directional buses usually cannot read and write simultaneously, system speed can be reduced in many applications requiring high I/O bandwidth. One solution to this problem has been to increase the number of I/Os and make a separate uni-directional bus for input and output lines, thus doubling the bandwidth. Uni-directional I/O buses increase chip cost by increasing the number of I/Os that have to exit the microprocessor chip and attach to second level packaging. More I/Os can also increase the cost of the system boards as well as the wiring complexity of a system using the microprocessor chip.
If a system needs performance it is usually appropriate to pay the increased cost to realize the increased performance. However, many times it is desirable to use a given chip architecture and design for several system level products. In these cases one does not want to pay for performance if it cannot be recovered in increased system sales or revenue. It would, however, be advantageous to use the total system volume to reduce overall manufacturing cost by achieving the economy of scale that comes with producing more units of a particular microprocessor chip design.
The present invention offers a solution to this problem by an alternate design of the I/O structure of the microprocessor chip.
The present invention discloses a microprocessor bus structure that can be optionally configured for high performance uni-directional buses or a lower performance bi-directional bus. A microprocessor chip is designed with internal processor uni-directional I/O buses. These buses are coupled to a selectively controlled device bi-directional I/O bus and an optionally wired device uni-directional input bus. In one mode of operation, the device uni- directional input bus is wired externally via first level packaging. A binary uni-directional enable line is also wired, at this time, that controls logic that disables the receivers of the device bi-directional I/O bus and enables coupling the receivers of the device uni-directional input bus to the processor uni-directional input bus. A binary bi-directional mode control line is also wired to enable the drivers in the device bi-directional bus. The microprocessor chip now has separate uni-directional buses for input and output wired from the processor to external devices via first level package wiring and printed circuit board interconnects. In another mode of operation, the device uni-directional input bus is not wired external to the chip and the binary uni-directional enable line is not selected and the uni-directional receivers are gated off. The device bi-directional I/O bus is coupled to the processor uni-directional I/O buses. The binary bi-directional mode control line remains under control of the processor which may selectively enable the drivers or the receivers of the device bi-directional I/O bus.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.